The present invention is directed to a method and apparatus for generating a correction signal in a digital clock recovery means upon attainment of a defined phase spacing between a digital signal and a first auxiliary data clock. The data clock represents a selection of one of a plurality of auxiliary clocks that changes with the phase spacing. The auxiliary clocks have the same frequency that is slightly higher or lower than the bit rate of the digital signal and have identical phase spacing relative to one another.
This method is related to two methods disclosed in U.S. Pat. No. 4,841,548 and German Patent Application No. P 37 36 351.4. In U.S. Pat. No. 4,841,548, a phase sensor emits a correction signal when the edge of the auxiliary data clock comes closer to an edge of the digital signal by less than a defined time spacing. A delay means is required for this purpose. In the second reference (German Patent Application No. P 37 36 351.4), the correction signal results when the effective edges of the digital signal and of a special clock that is likewise derived from an auxiliary clock coincide, this special clock having the same frequency as the auxiliary data clock and being phase-shifted by a defined value relative thereto.